This invention relates to a data processing system having pipeline arithmetic/logic units and, more particularly, to the fault processing in a data processing system which is suitable for handling vector instructions.
Vector instruction processing by a data processing system is carried out in the manner of implementing by a single instruction the same process for sets of data (also called "elements"), as is known in the art. The system generally employs a pipeline arithmetic/logic unit (ALU). The pipeline ALU consists of several stages, implementing the same arithmetic/logic operation specified by the instruction for elements which are entered successively at the clock interval and outputting operational results at the clock interval. The operational results are stored sequentially through the store data buffer into a memory (e.g., main storage).
In such a data processing system, if a fault occurs in the pipeline ALU, it is necessary for the system to suspend the storing of resultant data to the memory and reexecute the instruction. U.S. Pat. No. 4,318,172 discloses the fault processing, in which data once held in the store data buffer is discriminated to be capable or incapable of retry at the occurrence of the fault, and the instruction is reexecuted by invalidating the held data which is determined to be capable of retry or storing the held data which is determined to be incapable of retry in the memory. This method is effective for instructions each implementing an arithmetic/logic operation for a set of data and storing the result by itself. However, the above method is hardly applicable to the occurrence of a fault during the process of an instruction such as a vector instruction which implements the same processing for sets of data using a pipeline ALU and stores the results. Particularly, when it is intended to retry an element at which a fault has occurred, instead of reexecuting the whole instruction, the method involves difficult factors such as the determination of the element number to be resumed. It is prohibited for data processing systems to write the same address location of the main storage twice during one instruction execution, and it is necessary to resume the execution in compliance with this rule.